1. Field of the Invention
The present invention relates to a technique of stabilizing the output of a reference voltage generating circuit that is used for battery-driven portable telephone devices.
2. Description of the Related Art
The threshold value of a field effect transistor (hereinafter referred to as FET) varies with environmental temperature. To counter this problem, a reference voltage generating circuit that can output a stable reference voltage Vref in spite of changes in environmental temperature has been developed. In this reference voltage generating circuit, field effect transistors having gates of different conductivity types are combined to provide a circuit that outputs a first voltage (Vpn) having a negative temperature coefficient with respect to a change in environmental temperature, and field effect transistors having gates of the same conductivity type and different doped-impurity concentrations are combined to provide a circuit that outputs a second voltage (Vnn) having a positive temperature coefficient. The temperature coefficient of the first voltage is adjusted, and the adjusted first voltage and the second voltage are added so as to output the stable reference voltage Vref. Such a reference voltage generating circuit that utilizes the gate work function difference is disclosed in Japanese Laid-Open Patent Application No. 2001-284464, for example. Hereinafter, the process of flattening the deviation in the temperature coefficients will be referred to as the temperature characteristics compensation.
FIG. 15A illustrates the structure of a reference voltage generating circuit 110 that utilizes the gate work function difference. This circuit includes p-channel FETs 101 through 105, and resistors 106 and 107. The FETs 101, 102, 104, and 105 have the same substrate-doping and channel-doping impurity concentrations, and are formed in the n-well of a p-type substrate. The substrate potential of each transistor is set at the same value as the source potential.
The FET 101 has an n-type gate that is doped with a high-concentration impurity (hereinafter referred to simply as the high-concentration n-type gate), and the FET 102 has a p-type gate that is doped with a high-concentration impurity (hereinafter referred to simply as the high-concentration p-type gate). The FET 101 and the FET 102 are designed to have the ratio (S=W/L) of the channel width W to the channel length L at the same value.
The FET 104 has a high-concentration p-type gate, and the FET 105 has a p-type gate that is doped with a low-concentration impurity (hereinafter referred to simply as the low-concentration p-type gate). The FETs 104 and 105 are designed to have the same ratio (S=W/L) of the channel width W to the channel length L.
Potential is supplied to the gate of the FET 101 from a source follower circuit that includes a resistance dividing circuit formed with the FET 103 having a high-concentration p-type gate and the two resistors 106 and 107 that are connected in series. The gate of the FET 102 and the gate of the FET 103 are connected to each other. The source and the gate of the FET 103 are connected to each other. The gate of the FET 101 is connected to the connection point between the source of the FET 103 and the resistor 106 (the point P10 representing potential V10 in FIG. 15A). The drain of the FET 103 is connected to the gate of the FET 105.
The FET 102 has the source and the gate connected to each other, and functions as a constant current source to supply constant current to the FET 101, to which the FET 102 is series-connected. In this structure, the potential between the source and the gate of the FET 101 that is calculated by subtracting the potential V10 from power supply voltage Vcc is Vpn (=Vcc−V10). Meanwhile, potential V11 is represented as (the resistance value of the resistor 107/the resistance value of the resistor 106)×Vpn.
The FET 104 has the source and the gate connected to each other, and functions as a constant current source to supply constant current to the FET 105, to which the FET 104 is series-connected. With the potential between the source and the gate of the FET 105 being Vnn, the source potential V12 of the FET 105 is represented as V11+Vnn=(the resistance value of the resistor 107/the resistance value of the resistor 106)×Vpn+Vnn (=Vref).
The FET 101 and the FET 102 that are connected in series form a first power supply circuit that exhibits a negative temperature coefficient with respect to a variation in environmental temperature. Meanwhile, the FET 104 and the FET 105 that are connected in series form a second power supply circuit that exhibits a positive temperature coefficient with respect to a variation in environmental temperature. The resistance values of the resistor 106 and the resistor 107, which form the resistance dividing circuit in the source follower circuit, are adjusted by a trimming technique, for example. By doing so, the deviation in the negative temperature coefficient is adjusted, and the positive and negative temperature coefficients are cancelled. In this manner, a circuit that compensates the temperature characteristics and outputs a constant reference voltage Vref in spite of variations in environmental temperature is formed.
The deviations in the temperature coefficients of the respective circuits can be adjusted by changing the impurity concentrations of the high-concentration n-type gate of the FET 101, the high-concentration p-type gates of the FETs 102, 103, and 104, and the low-concentration p-type gate of the FET 105, as well as the resistance values of the resistors 106 and 107.
FIG. 15B illustrates the structure of a reference voltage generating circuit 120 that has a different structure from the reference voltage generating circuit 110. This reference voltage generating circuit 120 includes p-channel FETs 121 through 123, a FET 126, a FET 127, and resistors 124 and 125. The FETs 121, 122, 126, and 127 have the same substrate-doping and channel-doping impurity concentrations, and are formed in the n-well of a p-type substrate. The substrate potential of each transistor is set at the same value as the source potential.
The FET 121 has a high-concentration n-type gate, and the FET 122 has a high-concentration p-type gate. The FET 121 and the FET 122 are designed to have the ratio (S=W/L) of the channel width W to the channel length L at the same value.
The FET 126 has a high-concentration p-type gate, and the FET 127 has a low-concentration p-type gate. The FETs 126 and 127 are designed to have the same ratio (S=W/L) of the channel width W to the channel length L.
Potential is supplied to the gate of the FET 121 from a source follower circuit that includes a resistance dividing circuit formed with the FET 123 having a high-concentration p-type gate and the two resistors 124 and 125 that are connected in series. The gate of the FET 122 and the gate of the FET 123 are connected to each other. The source and the gate of the FET 123 are connected to each other. The gate of the FET 121 is connected to the connection point between the source of the FET 123 and the resistor 125 (the point P13 representing potential V13 in FIG. 15B). The contact point P15 between the resistors 124 and 125 is connected to the gate of the FET 126.
The FET 122 has the source and the gate connected to each other, and functions as a constant current source to supply constant current to the FET 121, to which the FET 122 is series-connected. In this structure, the potential between the source and the gate of the FET 121 that is calculated by subtracting the potential V13 from power supply voltage Vcc is Vpn (=Vcc−V13). Meanwhile, potential V14 is represented as Vcc−[(the resistance value of the resistor 124)×(the resistance value of the resistor 124+the resistance value of the resistor 125)×Vpn].
The FET 126 has the source and the gate connected to each other, and functions as a constant current source to supply constant current to the FET 127, to which the FET 126 is series-connected. With the potential between the source and the gate of the FET 127 being Vnn, the source potential V15 of the FET 127 is represented as Vcc−V14+Vnn=(the resistance value of the resistor 124/(the resistance value of the resistor 124+the resistance value of the resistor 125))×Vpn+Vnn (=Vref).
The FET 121 and the FET 122 that are connected in series form a first power supply circuit that exhibits a negative temperature coefficient with respect to a variation in environmental temperature. Meanwhile, the FET 126 and the FET 127 that are connected in series form a second power supply circuit that exhibits a positive temperature coefficient with respect to a variation in environmental temperature. The resistance values of the resistor 124 and the resistor 125, which form the resistance dividing circuit in the source follower circuit, are adjusted by a trimming technique, for example. By doing so, the deviation in the negative temperature coefficient is adjusted, and a circuit that compensates the temperature characteristics and outputs a constant reference voltage Vref in spite of variations in environmental temperature is formed. The deviations in the temperature coefficients of the respective circuits can be adjusted by changing the impurity concentrations of the high-concentration p-type gate of the FET 122 and the low-concentration n-type gate of the FET 127, as well as the resistance values of the resistors 124 and 125.
As is apparent from the comparison between the reference voltage generating circuit 110 (hereinafter referred to simply as the circuit 110) and the reference voltage generating circuit 120 (hereinafter referred to simply as the circuit 120), there are no characteristic differences between the first-stage circuit that is formed with the FET 101 and the FET 102 of the 110 and the first-stage circuit that is formed with the FET 121 and the FET 122 of the circuit 120, and between the second-stage circuit that is formed with the FET 103 and the resistors 106 and 107 of the circuit 110 and the second-stage circuit that is formed with the FET 123 and the resistors 124 and 125. The potential difference between the two ends of the resistor 106 of the circuit 110, and the potential difference between the two ends of the resistors 124 and 125 of the circuit 120 are both Vpn. Accordingly, the voltage Vds1 between the drain and the source of each of the FET 101 of the circuit 110 and the FET 121 of the circuit 120 is determined by Vpn+Vgs (the voltage between the source and the gate of each of the FET 103 of the circuit 110 and the FET 123 of the circuit 120).
Here, the voltage Vds2 between the drain and the source of each of the FET 102 of the circuit 110 and the FET 122 of the circuit 120 is determined by the equation: Vds2=Vcc−Vds1. As is apparent from this equation, only the voltage Vds2 between the drain and the source of each of the FET 102 of the circuit 110 and the FET 122 of the circuit 120 is affected by a variation in Vcc.
FIG. 17 shows the Vg-Id characteristics of the FET 101 and the FET 102 of the circuit 110 when the power supply voltage Vcc varied. As the power supply voltage Vcc becomes higher, the Vg-Id characteristics of the FET 102 vary, and Vpn increases by ΔVpn. Although not shown, the Vg-Id characteristics of the FET 121 and the FET 122 of the circuit 120 are the same as the Vg-Id characteristics of the FET 101 and the FET 102 of the circuit 110 in that as the power supply voltage Vcc becomes higher, Vpn increases by ΔVpn.
As for the third-stage circuit that is formed with the FET 104 and the FET 105 of the circuit 110 and the third-stage circuit that is formed with the FET 126 and the FET 127 of the circuit 120, the FET 104 and the FET 126 serve as constant current sources to generate Vnn between the source-gate voltage of each of the FET 104 and the FET 126 and the source-gate voltage of each of the FET 105 and the FET 127. While the source-gate voltage Vgs of the FET 104 is 0, the source-gate voltage Vgs of the FET 126 is determined by (the resistance value of the resistor 124)/(the resistance value of the resistor 124+the resistance value of the resistor 125)×Vpn.
Accordingly, Vpn varies in either of the circuits 110 and 120. However, only in the circuit 120 illustrated in FIG. 15B, the Vpn variation affects the constant current source of the third-stage circuit. As the source-gate voltage Vgs of the constant current source varies, the operating point moves, resulting in a variation in Vnn. In short, when the power supply voltage Vcc varies, only Vpn varies in the circuit 110, but both Vpn and Vnn vary in the circuit 120. From this fact, the reference voltage generating circuit 110 illustrated in FIG. 15A is the more stable circuit.
FIGS. 16A and 16B show Vref variations with respect to variations in the power supply voltage Vcc (hereinafter referred to as the input stability) and Vref variations with respect to temperature variations (hereinafter referred to as the temperature characteristics) in each of the circuits 110 and 120. The circuits 110 and 120 have the same ideal values for the temperature characteristics. The input stability indicates the stability of the value of the reference voltage Vref to be output with respect to a variation in the value of the power supply voltage Vcc. The more stable the reference voltage Vref is, the closer the value is to the ideal value. As for the temperature characteristics, the value becomes closer to the ideal value as the deviations of the temperature coefficient become more flat. In FIGS. 16A and 16B, the input stability and the temperature characteristics of each of the circuits 110 and 120 having polycrystalline silicon resistors are shown by ♦, and the ideal values are shown by ▴.
In the case with the ideal resistors indicated by ▴, the input stability of the circuit 110 is higher than the input stability of the circuit 120, and the temperature characteristics are the same between the circuits 110 and 120. In the case with resistors made of polycrystalline silicon, however, the input stability and the temperature characteristics of the circuit 110 are much poorer than the ideal values, as indicated by ♦.
The reasons for this can be considered as follows. In the case of a resistor made of polycrystalline silicon, the carrier density in the polycrystalline silicon is affected by the potential difference between conductors such as metal wires in contact with a surface of the polycrystalline silicon and a substrate insulator or a well in contact with the other surface of the polycrystalline silicon. As a result, the resistance value varies.
In the case where the potential of the resistor made of polycrystalline silicon and the potential of the conductor connected to the resistors are both 0 v, for example, the resistor made of polycrystalline silicon exhibits a desired value, because there is not a potential difference between the resistor and the conductor.
If the potential of the polycrystalline silicon resistor is increased from 0 v to 1 v while the potential of the conductor remains 0 v, the potential difference (ΔV) between the polycrystalline silicon resistor and the conductor becomes −1 v, which is a negative value. If the polycrystalline silicon resistor is an n-type resistor, a depletion layer is formed in the resistor, and the resistance value becomes greater.
Under the bias condition that the potential difference (ΔV) is a positive value, an accumulation layer is formed in the resistor. As a result the resistance value of the polycrystalline silicon resistor becomes smaller.
FIG. 18A shows the potential difference (ΔV) between the resistances 106 and 107 and the n-well of the circuit 110. FIG. 18B shows the potential difference (ΔV) between the resistances 124 and 125 and the n-well of the circuit. The potential difference (ΔV) with the n-well that is a conductor in contact with any of the resistors 106, 124, and 125 is not affected by the Vcc variation. However, the potential difference (ΔV) between the resistor 107 and the n-well varies with the Vcc variation. In short, the resistance value of the resistor 107 varies as the power supply voltage Vcc varies. As a result, the potential V11 that is represented as (the resistance value of the resistor 107)/(the resistance value of the resistor 106)×Vpn varies, and so does the value of the reference voltage Vref. In the case with resistors made of polycrystalline silicon, the circuit 110 exhibits poorer values than the circuit 120 with respect to the ideal values, as shown in FIG. 16A.
Any depletion layer or any accumulation layer caused in the resistors has dependency on temperature. The temperature dependency becomes greater, as the potential difference (ΔV) becomes greater. Since the resistor 107 exhibits the greatest potential difference (ΔV) among the resistors 106, 107, 124, and 125, the circuit 110 is farther away from the ideal values than the circuit 120 is from the ideal values, as shown in FIG. 16B.